Development of an economical lapping process

Konneh, Mohamed and Tamsir, Afzeri and Triblas Adesta, Erry Yulian (2012) Development of an economical lapping process. Advanced Materials Research, 472-47. pp. 2348-2353. ISSN 1022-6680

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Abstract

The manufacturing of silicon wafers in particular involves numerous processes such as grinding, lapping, and polishing of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. This paper presents the development of a low cost lapping process, the process tried out on thin silicon chips that generated fracture-free with mirror-like surfaces of low roughness values and reasonably high degree of flatness.

Item Type:	Article (Journal)
Additional Information:	4486/28463
Uncontrolled Keywords:	Lapping, lapping pressure, silicon, flatness, surface roughness and integrity, RSM
Subjects:	T Technology > TJ Mechanical engineering and machinery > TJ1125 Machine shops and machine shop practice
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering > Department of Manufacturing and Materials Engineering
Depositing User:	Dr Mohamed Konneh
Date Deposited:	14 Jan 2013 15:50
Last Modified:	18 Aug 2015 14:15
URI:	http://irep.iium.edu.my/id/eprint/28463

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