Design of 0.13um CMOS multi-valued analog to digital converter

Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz and Rahman, Md. Ataur (2012) Design of 0.13um CMOS multi-valued analog to digital converter. In: International Conference on Computer and Communication Engineering (ICCCE 2012), 3-5 July 2012, Seri Pacific Hotel Kuala Lumpur.

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Abstract

A multi-valued logic outputs for analog to digital (ADC) have been implemented in this paper. The use of multiple-valued logic outputs for ADC design offers the possibility of an overall reduction in circuit complexity and size. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design implements current mode ADC architecture and is simulated using the model parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable performance parameters in terms of response, low power consumption, and a sampling rate of 500kHz at a supply voltage of 1.3V was achieved. The ADC design is suitable for digital wireless communication applications such as ultra wideband (UWB) and the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

Item Type:	Conference or Workshop Item (Invited Papers)
Additional Information:	4575/26288
Uncontrolled Keywords:	Multi-valued; ADC; CMOS process
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering > Department of Electrical and Computer Engineering Kulliyyah of Engineering > Department of Mechanical Engineering
Depositing User:	Prof. Dr. AHM Zahirul Alam
Date Deposited:	14 Dec 2012 08:38
Last Modified:	14 Jun 2017 10:18
URI:	http://irep.iium.edu.my/id/eprint/26288

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