Modeling of the reliability baseline for process control monitoring kerf structures

Izuddin, Ismah and Kamaruddin, Mohd. Hanif and Nordin, Anis Nurashikin (2011) Modeling of the reliability baseline for process control monitoring kerf structures. In: 2011 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 28-30 September, Kota Kinabalu, Malaysia.

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Abstract

We present the Product Chip Monitor-Wafer Level Reliability (PCM-WLR) model and characteristic of a 45nm thick gate-oxide (GOX), trench DMOS technology. The process control monitor (PCM) refers to the suite of test structures usually placed in the scribe line (alternatively named kerf, street or test key) separating product die on the wafer. The motivation of this work is to establish the baseline of the dielectric and device reliability for the kerf PCM structure that will enhance the capability to perform lot disposition in the event of PCM test out-of-control (OOC). Different test structures will be stressed and correlation study is performed with existing models. The experiment was performed at Infineon Technologies Kulim Failure Analysis Lab and that test wafers were fabricated by Infineon Technologies.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	3239/19885
Uncontrolled Keywords:	Electric breakdown , Electron traps , Logic gates , Silicon , Stress , Temperature measurement , Voltage measurement
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering
Depositing User:	Dr. Anis Nurashikin Nordin
Date Deposited:	17 Feb 2012 15:36
Last Modified:	17 Feb 2012 15:40
URI:	http://irep.iium.edu.my/id/eprint/19885

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