Development of a low cost lapping process

Konneh, Mohamed and Amin, A. K. M. Nurul and Afzeri, Afzeri and Ahmarofi, A. A. (2009) Development of a low cost lapping process. In: International Conference on Advances in Materials & Processing Technology (AMPT 2009), 26-29 Oct., 2009, Kuala Lumpur.

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Abstract

Conventional process of producing silicon based products uses large work-piece and it is difficult to attain high flatness of the finished surface. Thus it is not unusual to find it difficult to fine finish small area of planar surfaces and attain high degree of flatness on the finished surfaces. The manufacturing of silicon wafers in particular involves numerous grinding, lapping, and polishing processes of large diameter wafers employing expensive equipment in order to produce the required optical quality and damage-free surfaces. In the finishing of thin silicon chips for making IC chips especially, it is difficult to lap and/polish the substrate and obtain low surface integrity, surface finish and at the same time generate flat planar surfaces. Therefore the understanding of lapping process is very essential for economic manufacture and process improvement of thin silicon chips. A low cost lapping process has been developed, the process tried out on thin silicon chips that generated damage-free with a mirror-like surfaces of low roughness values and reasonably high degree of flatness.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	4486/17035
Uncontrolled Keywords:	Lapping, lapping pressure, silicon IC chip, flatness, surface roughness, RSM
Subjects:	T Technology > TS Manufactures
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering > Department of Manufacturing and Materials Engineering
Depositing User:	Dr. A.K.M. Nurul Amin
Date Deposited:	26 Jan 2012 10:46
Last Modified:	03 Feb 2012 12:48
URI:	http://irep.iium.edu.my/id/eprint/17035

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