Encryption in TECB mode: modeling, simulation and synthesis

Ibrahimy, Muhammad Ibn (2007) Encryption in TECB mode: modeling, simulation and synthesis. In: Asia Simulation Conference, 2007, 10-12 October, 2007, Seoul, Korea.

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Abstract

The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software coun-terpart.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	4637/36640 DOI: 10.1007/978-3-540-77600-0_23 Print ISBN 978-3-540-77599-7 Online ISBN 978-3-540-77600-0
Uncontrolled Keywords:	Encryption in TECB mode, modeling, simulation and synthesis
Subjects:	T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User:	Dr Muhammad Ibrahimy
Date Deposited:	16 May 2014 15:23
Last Modified:	16 May 2014 15:54
URI:	http://irep.iium.edu.my/id/eprint/36640

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