FPGA implementation of RSA encryption engine with flexible key size

Ibrahimy, Muhammad Ibn and Reaz, Mamun Bin Ibne and Asaduzzaman, Khandaker and Chowdhury, Md. Sazzad Hossien (2007) FPGA implementation of RSA encryption engine with flexible key size. International Journal of Communications, 1 (3). pp. 107-113.

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Abstract

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.

Item Type:	Article (Journal)
Additional Information:	4637/29540
Uncontrolled Keywords:	RSA, FPGA, Communication, Security, VHDL.
Subjects:	T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering
Depositing User:	Dr Muhammad Ibrahimy
Date Deposited:	28 Mar 2013 11:02
Last Modified:	28 Mar 2013 11:02
URI:	http://irep.iium.edu.my/id/eprint/29540

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