FPGA implementation of light rail transit fare card controller using VHDL

Ullah, Mohammad Habib and Priantoro, Akhmad Unggul and Hassan, M. A. and Uddin, Md. Jasim (2009) FPGA implementation of light rail transit fare card controller using VHDL. European Journal of Scientific Research, 36 (1). pp. 30-40. ISSN 1450-216X, 1450-202X

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Abstract

In this paper a new and better fare system is introduced. One part of the Light Rail Transit (LRT) system that needs to be upgraded is the fare card controller because smart card (similar to Touch & Go) will replace the existing paper ticket. Altera Quartus II Web Edition software tool is used to synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. According to the result in simulation and implementation in the FPGA (Field Programmable Gate Array), it can be said that the designed model is working as expected.

Item Type:	Article (Journal)
Additional Information:	4876/12753
Uncontrolled Keywords:	Fair card controller; FPGA; LR; RTL; VHDL
Subjects:	T Technology > T Technology (General) T Technology > TA Engineering (General). Civil engineering (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering
Depositing User:	Nur' Aini Abu Bakar
Date Deposited:	16 Feb 2012 08:59
Last Modified:	16 Feb 2012 08:59
URI:	http://irep.iium.edu.my/id/eprint/12753

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