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Design of a multi valued current mode comparator

Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz (2011) Design of a multi valued current mode comparator. Australian Journal of Basic and Applied Sciences, 5 (10). pp. 662-666. ISSN 1991-8178

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Abstract

In this paper, a low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented. Existing MVL comparator circuits consume high power. The circuit presented in this paper low power. It has been simulated with PSPICE using the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13um CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators designed in these technologies are discussed. The comparator design is suitable for the needs of mixed signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

Item Type: Article (Journal)
Additional Information: 4575/7353
Uncontrolled Keywords: Quaternary, CMOS, MVL, comparator.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User: Dr AHM Zahirul Alam
Date Deposited: 21 Nov 2011 15:04
Last Modified: 14 Dec 2012 08:55
URI: http://irep.iium.edu.my/id/eprint/7353

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