Network-on-chip implementation of hierarchical torus network

Rahman, M.M. Hafizur and Ray, Sajib and Md. , Rabiul Awal (2013) Network-on-chip implementation of hierarchical torus network. In: 3rd International Conference on Software Engineering and Computer Systems (ICSECS - 2013), 20 - 22 August 2013, Kuantan, Pahang.

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Abstract

The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies. With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	6724/31743
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Information and Communication Technology > Department of Computer Science Kulliyyah of Information and Communication Technology > Department of Computer Science
Depositing User:	Dr. M.M. Hafizur Rahman
Date Deposited:	24 Sep 2013 15:40
Last Modified:	24 Sep 2013 15:40
URI:	http://irep.iium.edu.my/id/eprint/31743

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