IIUM Repository

Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process

Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz (2012) Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process. Science Series Data Report, 4 (3). (1-8). ISSN 1307-119X

[img] PDF (SDR) - Published Version
Restricted to Repository staff only

Download (99kB) | Request a copy


The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (ADC) circuit is presented in this paper. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design implements pipeline ADC architecture and is simulated using the model parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable qualities in terms of response, low power consumption, and a sampling rate of 500kz at a supply voltage of 1.3 V. The ADC design is suitable for the needs of mixed-signal integrated circuit design and implemented as a conversion circuit for systems based on multi valued logic design.

Item Type: Article (Journal)
Additional Information: 4575/24248
Uncontrolled Keywords: MVL, ADC, CMOS
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User: Prof. Dr. AHM Zahirul Alam
Date Deposited: 11 Jun 2012 11:38
Last Modified: 30 Nov 2020 10:00
URI: http://irep.iium.edu.my/id/eprint/24248

Actions (login required)

View Item View Item


Downloads per month over past year