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Design of a 5GHz phase-locked loop

Mohamad Ashari, Zainab and Nordin, Anis Nurashikin and Ibrahimy, Muhammad Ibn (2011) Design of a 5GHz phase-locked loop. In: Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on, 28-30 Sept., 2011, Kota Kinabalu, Malaysia.

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Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. PLLs are often used in communication technology to implement a variety of functions such as clock recovery, frequency multiplication, and clock synchronization. This paper presents the design and simulation results of PLL with low jitter performance. The key goal is to design and develop an analog PLL circuit for 5 GHz clock data recovery circuit. The PLL comprises of a phase frequency detector (PFD), low pass filter, voltage controlled oscillator (VCO), and feedback divider. In this work, analog mixed-signal architecture of PLL is simulated using hardware discipline modeling language, Verilog-AMS HDL. Multilingual and Mixed-Signal simulator SMASH software has been used for the Verilog-AMS design. A 5 GHz PLL with less jitter was successfully designed in this work.

Item Type: Conference or Workshop Item (Full Paper)
Additional Information: 3239/15122
Uncontrolled Keywords: Phase-locked loop (PLL), jitter, Verilog-AMS, Phase Frequency Detector, Low-pass Filter, and Voltage-controlled Oscillator
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices > TK7885 Computer engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User: Dr. Anis Nurashikin Nordin
Date Deposited: 20 Jan 2012 13:27
Last Modified: 06 May 2012 18:04
URI: http://irep.iium.edu.my/id/eprint/15122

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