Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

Rahman, M.M. Hafizur and Ghosh, Manas and Horiguchi, Susumu (2006) Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns. In: Electrical and Computer Engineering, 2006. ICECE '06. International Conference on , 19-21 Dec. 2006 , Dhaka, Bangladesh.

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Abstract

In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using the proposed routing algorithm. We evaluate the inter-processor communication performance of HTN, H3D-mesh, TESH, mesh, and torus network by computer simulation. It is shown that the inter-processor communication performance of the HTN is better than that of the H3D-mesh, TESH, mesh, and torus networks.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	6724/8227
Uncontrolled Keywords:	H3D-mesh , HTN , TESH , bit-flip traffic patterns , computer simulation , deadlock-free routing , dimension order routing , hierarchical torus network , inter-processor communication
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Information and Communication Technology > Department of Computer Science Kulliyyah of Information and Communication Technology > Department of Computer Science
Depositing User:	Dr. M.M. Hafizur Rahman
Date Deposited:	19 Dec 2012 12:48
Last Modified:	19 Dec 2012 12:48
URI:	http://irep.iium.edu.my/id/eprint/8227

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