Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches

Olanrewaju, Rashidah Funke and Khan, Burhan Ul Islam and Khan, Abdul Raouf and Yaacob, Mashkuri and Alam, Md. Moktarul (2018) Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches. International Journal of Grid and Utility Computing, 9 (4). pp. 307-321. ISSN 1741-847X E-ISSN 1741-8488

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Abstract

The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache. The current study is intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate (WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the conventional LRU techniques.

Item Type:	Article (Journal)
Additional Information:	6796/70884
Uncontrolled Keywords:	cache replacement algorithm; field assisted STT-MRAM; error rate; L2 caches
Subjects:	T Technology > T Technology (General) > T10.5 Communication of technical information
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User:	Dr. Rashidah Funke Olanrewaju
Date Deposited:	07 Mar 2019 15:16
Last Modified:	12 Jul 2019 15:54
URI:	http://irep.iium.edu.my/id/eprint/70884

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