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Design consideration for successful delay fault testing in SOC

Dass, Sreedharan Baskara and Hassan Abdalla Hashim, Aisha (2004) Design consideration for successful delay fault testing in SOC. In: 3rd International Conference on Electrical & Computer Engineering ICECE 2004, 28th-30th December 2004, Dhaka, Bangladesh.

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Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and ready. The test chip was designed scan ready but with no delay fault testing constructs.

Item Type: Conference or Workshop Item (Invited Papers)
Additional Information: 2523/50147
Uncontrolled Keywords: Delay Fault Testing,
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Kulliyyah of Engineering
Depositing User: Prof. Dr. Aisha Hassan Abdalla Hashim
Date Deposited: 02 Jun 2016 10:07
Last Modified: 02 Jul 2020 14:53
URI: http://irep.iium.edu.my/id/eprint/50147

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