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FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard

Shyamsi, M. and Ibrahimy, Muhammad Ibn and Motakabber, S. M. A. and Ahsan, M. R. (2015) FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard. Journal of Communications Technology, Electronics and Computer Science, 1. pp. 1-6. ISSN 2457-905X

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis, etc. Implementation of floating-point multiplication is handy and easy for high level language. However, it is a challenging task to implement a floating-point multiplication in hardware level or in low level language due to the complexity of algorithms. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.

Item Type: Article (Journal)
Additional Information: 4637/45503
Uncontrolled Keywords: Floating-point; Verilog HDL; Carry Look Ahead Adder; Ripple Carry Adder; FPGA
Subjects: T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering
Depositing User: Dr Muhammad Ibrahimy
Date Deposited: 02 Nov 2015 15:02
Last Modified: 06 Mar 2017 16:24
URI: http://irep.iium.edu.my/id/eprint/45503

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