Fault tolerant hardware for high performance signal processing

Erdogan, S. S. and Shaneyfelf, Ted and Geok, See Ng and Abdul Rahman, Abdul Wahab (2008) Fault tolerant hardware for high performance signal processing. In: The Fourth Advanced International Conference on Telecommunications AICT '08, 8-13 June 2008, Athens, Greece.

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Abstract

The approach described in this paper uses an array of Field Programmable Gate Array (FPGA) devices to implement a fault tolerant hardware system that can be compared to the running of fault tolerant software on a traditional processor. Fault tolerance is achieved is achieved by using FPGA with on the fly partial programmability feature. Major considerations while mapping to the FPGA includes the size of the area to be mapped and communication issues related to their communication. Area size selection is compared to the page size selection in Operating System Design. Communication issues between modules are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files is discussed.

Item Type:	Conference or Workshop Item (UNSPECIFIED)
Additional Information:	6145/38157 DOI: 10.1109/AICT.2008.41
Uncontrolled Keywords:	FPGA, Fault Tolerance, Signal Processing, HDL, communication
Subjects:	T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Information and Communication Technology > Department of Computer Science Kulliyyah of Information and Communication Technology > Department of Computer Science
Depositing User:	Prof Abdul Wahab Abdul Rahman
Date Deposited:	18 Sep 2014 13:28
Last Modified:	16 Dec 2020 23:52
URI:	http://irep.iium.edu.my/id/eprint/38157

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