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Development of an efficient algorithm for fetal heart rate detection: a hardware approach

Ibrahimy, Muhammad Ibn and Reaz, Mamun Bin Ibne and Mohd Ali, Mohd Alauddin and T., H. Khoon and Ismail, Ahmad Faris (2006) Development of an efficient algorithm for fetal heart rate detection: a hardware approach. In: 5th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems, 2006, 16-18 April, 2006, Hangzhou, China.

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An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on cross-correlation, adaptive thresholding and statistical properties in the time domain. The algorithm was initially developed and simulated in Visual C++. Once the functionality is verified, it is then converted in VHDL - hardware description language for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an error percentage of around ±0.3% and ±0.5% for the detection of maternal and fetal heart rate respectively.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: 4637/36661
Uncontrolled Keywords: Fetal Heart Rate, Electro cardiogra m , VHDL, FPG A
Subjects: T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button): Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User: Dr Muhammad Ibrahimy
Date Deposited: 21 May 2014 14:54
Last Modified: 15 Jun 2020 14:37
URI: http://irep.iium.edu.my/id/eprint/36661

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