A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design

Azman, Amelia Wong and Bigdeli, Abbas and Mohd Mustafah, Yasir and Biglari-Abhari, Morteza and Lovell, Brian (2010) A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design. In: 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP , 7 - 9 July 2010, Rennes, France.

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Abstract

In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework.

Item Type:	Conference or Workshop Item (Full Paper)
Additional Information:	4858/28300 (ISBN: 978-1-4244-6966-6)
Uncontrolled Keywords:	Bayesian methods;Computer networks;Design engineering;Field programmable gate arrays;Hardware design languages;Laboratories;Neural networks;Open source software;Process design;Processor scheduling;
Subjects:	T Technology > T Technology (General)
Kulliyyahs/Centres/Divisions/Institutes (Can select more than one option. Press CONTROL button):	Kulliyyah of Engineering
Depositing User:	Dr Yasir Mohd Mustafah
Date Deposited:	18 Sep 2013 10:42
Last Modified:	18 Sep 2013 10:43
URI:	http://irep.iium.edu.my/id/eprint/28300

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