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Design of a current comparator for quaternary multi valued analog to digital converter

Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz and Rahman, Mohammed Ataur (2011) Design of a current comparator for quaternary multi valued analog to digital converter. In: 2011 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 28-30 September, Kota Kinabalu, Malaysia.

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Abstract

A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE using the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13 μm CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators designed in these technologies are discussed. The comparator design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

Item Type: Conference or Workshop Item (Full Paper)
Additional Information: 4575/11857 (Print ISBN: 978-1-61284-844-0)
Uncontrolled Keywords: quartenary, CMOS, MVL, comparator
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Kulliyyahs/Centres/Divisions/Institutes: Kulliyyah of Engineering
Kulliyyah of Engineering > Department of Electrical and Computer Engineering
Depositing User: Dr Ataur Rahman
Date Deposited: 13 Jan 2012 12:16
Last Modified: 14 Dec 2012 08:57
URI: http://irep.iium.edu.my/id/eprint/11857

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